The transfer clock frequency for 3-wire serial I communication can be calculated by the following expressions.
(1) For Master
(Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) For Slave
(Transfer clock frequency) = {Frequency of serial clock (fSCK) supplied by master}Note [Hz]
Note :The permissible maximum transfer clock frequency is fMCK/6.
Remark :The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register (SDRmn) (0000000B to 1111111B) and therefore is 0 to 127. The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn).