How to leverage the UART function of digital IC XDPL series?
How to leverage the UART function of digital IC XDPL series?
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A UART (Universal Asynchronous Receiver Transmitter) is a piece of logic that sends and receives data on a serial port.
How to leverage the UART function of digital IC XDPL series?
How to leverage the UART function of digital IC XDPL series?
Read lessIn Bootloader my UART is not working, while I have checked that all UART register is same . I got the garbage data on UART.
In Bootloader my UART is not working, while I have checked that all UART register is same . I got the garbage data on UART.
Read lessHi Raja, First check if your baudrate is not changed by using SPS1 Register. If SPS1 register is not changed, then Please try to check your MCU clock first , it may be changed, Not call in systeminit function because in bootloader code, cgc_create() function already call. You can comment this cgc_crRead more
Hi Raja,
First check if your baudrate is not changed by using SPS1 Register. If SPS1 register is not changed, then Please try to check your MCU clock first , it may be changed, Not call in systeminit function because in bootloader code, cgc_create() function already call.
You can comment this cgc_create() function in systeminit file, then it will work.
Please feel free to write us for further support.
Thanks & Regards
Shivali Singh
Application Engineer
See lessI use Renesas R7F7015813AFP-C.RLIN3 work in UART mode, “For performing half-duplex communication , the LIN/UART interface(in UART mode) have the support transmission start wait function”(19.8.1.7 in datasheet), does UART work in half-duplex? Does it support full-duplex?
I use Renesas R7F7015813AFP-C.RLIN3 work in UART mode, “For performing half-duplex communication , the LIN/UART interface(in UART mode) have the support transmission start wait function”(19.8.1.7 in datasheet), does UART work in half-duplex? Does it support full-duplex?
Read lessRenesas RH850, UART, DMA, 1.5Mbps, TX&RX are used together. The receiver will not work after receiving several frames of data. It must be re-initialized, but it will stop working soon, but TX or RX can be used alone.
Renesas RH850, UART, DMA, 1.5Mbps, TX&RX are used together. The receiver will not work after receiving several frames of data. It must be re-initialized, but it will stop working soon, but TX or RX can be used alone.
Read lessI guess you still need to include more details in order to fix your issue. However, I suggest you submit a ticket to Renesas Technical Support regarding your issue as information regarding automotive devices is not really shared in public. Also, please use your company email when submitting ticketsRead more
I guess you still need to include more details in order to fix your issue. However, I suggest you submit a ticket to Renesas Technical Support regarding your issue as information regarding automotive devices is not really shared in public. Also, please use your company email when submitting tickets to Renesas Technical Support.
See lessHow to connect or access UART with .dp vision Gen 2 with XDPL series IC.
How to connect or access UART with .dp vision Gen 2 with XDPL series IC.
Read lessHi Manoj. Connection needs to be done b/w .dp Vision Gen2 Pin 2,3 &4. Where • Pin 4 is VCC • Pin 2 is GND • Pin 3 is UART Connect accordingly.
Hi Manoj.
Connection needs to be done b/w .dp Vision Gen2 Pin 2,3 &4. Where
• Pin 4 is VCC
• Pin 2 is GND
• Pin 3 is UART
Connect accordingly.
What are the settings required to achieve 1Mbps speed while working on Renesas RAL21. I am working on Renesas RA2L1, 48 pin controller part#R7FA2L1A93CFL with FSP version 3.5.0. I am unable to achieve 1Mbps speed.
What are the settings required to achieve 1Mbps speed while working on Renesas RAL21. I am working on Renesas RA2L1, 48 pin controller part#R7FA2L1A93CFL with FSP version 3.5.0. I am unable to achieve 1Mbps speed.
Read lessI have attached workspace for UART done on RA2L1 and FSP v3.5.0 to set BR- 1000000. Please make sure your USB to TTL convertor supported with 1MBps speed. You need to see Baud rate modulation is enabled and set the BR to 1000000, refer below snap Please go through the HW manual of RA2L1 to check theRead more
I have attached workspace for UART done on RA2L1 and FSP v3.5.0 to set BR- 1000000. Please make sure your USB to TTL convertor supported with 1MBps speed.
You need to see Baud rate modulation is enabled and set the BR to 1000000, refer below snap
Please go through the HW manual of RA2L1 to check the UART error rate calculation.
See less
There are basically two way to change the UART baud rate at run-time. It depends how you allocated the UART. If you allocated by PDL-method (ie. In the PSoC Creator TopDesign or Modustoolbox Device Configurator [design.modus]) then use the PDL SysClk API calls: Configure Baud Rate To get the UARTRead more
There are basically two way to change the UART baud rate at run-time. It depends how you allocated the UART.
If you allocated by PDL-method (ie. In the PSoC Creator TopDesign or Modustoolbox Device Configurator [design.modus]) then use the PDL SysClk API calls:
Configure Baud Rate
To get the UART to operate with the desired baud rate, the clk_scb frequency and the oversample must be configured. Use the SysClk (System Clock) driver API to configure clk_scb frequency. Set the oversample parameter in configuration structure to define the number of the SCB clocks within one UART bit-time.
* For clk_peri = 50 MHz, select divider value 36 and get SCB clock = (50 MHz / 36) = 1,389 MHz.
* Select Oversample = 12. These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
*/
Cy_SysClk_PeriphSetDivider (UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER, 35UL);
Cy_SysClk_PeriphEnableDivider(UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER);
Refer to the technical reference manual (TRM) section UART sub-section Clocking and Oversampling to get information about how to configure the UART to run with desired baud rate.
link: file:///C:/Program%20Files%20(x86)/Cypress/PDL/3.1.1/doc/pdl_api_reference_manual/html/group__group_…
If you allocated the UART by the HAL-method use:
cyhal_uart_set_baud() link: Hardware Abstraction Layer (HAL)
See less