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SPI is a low-level 3 or 4 wire serial bus interface with clock (SCLK), data in (MISO) and data out (MOSI). The fourth wire is a Slave Select to uniquely select a device on the bus. This signal is us…

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ashishgawade
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ashishgawade
Asked: December 8, 2022In:
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Hello, I need to use both UART and SPI interface, FX3’s SPI interface and UART interface are shared, now my SPI is connected to FLASH, I need to power on through SPI FLASH, so I can not use its UART ...Read more

Hello, I need to use both UART and SPI interface, FX3’s SPI interface and UART interface are shared, now my SPI is connected to FLASH, I need to power on through SPI FLASH, so I can not use its UART function, but FX3 has” 16- bit data bus UART SPI I2S” mode. In this mode, UART is mapped to GPIO46-49. Can I use the following settings to enable me to use both UART and SPI FLASH BOOT?

io_cfg.isDQ32Bit = CyFalse;

io_cfg.s0Mode = CY_U3P_SPORT_INACTIVE;
io_cfg.s1Mode = CY_U3P_SPORT_INACTIVE;
io_cfg.useUart = CyTrue;
io_cfg.useI2C = CyFalse;
io_cfg.useI2S = CyFalse;
io_cfg.useSpi = CyTure;
io_cfg.lppMode = CY_U3P_IO_MATRIX_LPP_DEFAULT;
/* No GPIOs are enabled. */
io_cfg.gpioSimpleEn[0] = 0;
io_cfg.gpioSimpleEn[1] = 0x08000000;
io_cfg.gpioComplexEn[0] = 0;
io_cfg.gpioComplexEn[1] = 0;

And, can I still use the virtual COM port function of the UART in this mode?

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bootflashfx3gpio46spiuart
  1. vikas Nagpal

    Hi, You can use the" 16- bit Data Bus UART SPI I2S" configuration to use both UART and SPI. Please refer to the available GPIOs for that mode in Table 7 of the FX3 datasheet. As mentioned in the table, you must choose the proper GPIO if you want to use some GPIOs. If you want to use I2S GPIOs you haRead more

    Hi,

    You can use the” 16- bit Data Bus UART SPI I2S” configuration to use both UART and SPI. Please refer to the available GPIOs for that mode in Table 7 of the FX3 datasheet. As mentioned in the table, you must choose the proper GPIO if you want to use some GPIOs. If you want to use I2S GPIOs you have to override using CyU3PDeviceGpioOverride.

    Yes, the virtual COM port will work if you use the below configuration.

    Thanks

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nidhi singh
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nidhi singh
Asked: September 26, 2022In:
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RA6T2 Internal Flash?

Hi, I am curious about what kind of the internal flash of RA6T2 is? Is it NOR flash or NAND flash? According to the program and erase size, it seems to be NOR flash? still, what’s the physical interface of the flash? ...Read more

Hi,

I am curious about what kind of the internal flash of RA6T2 is? Is it NOR flash or NAND flash?
According to the program and erase size, it seems to be NOR flash?

still, what’s the physical interface of the flash? Does it use the SPI or other?
If it was NOR flash.Thanks

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flashinternalnorra6t2renesasRenesas Microcontrollerspi
  1. vikas Nagpal

    RA6T2 uses the Renesas proprietary Metal Oxide Nitride Oxide Semiconductor( MONOS) flash technology, it's neither NOR nor NAND. You can search the general web or the Renesas web pages and find information about this. The interface is a direct register grounded via the flash application command interRead more

    RA6T2 uses the Renesas proprietary Metal Oxide Nitride Oxide Semiconductor( MONOS) flash technology, it’s neither NOR nor NAND. You can search the general web or the Renesas web pages and find information about this.

    The interface is a direct register grounded via the flash application command interface( FACI). From the RA6T2 hardware U/ M
    The FCU( flash control unit) controls the programming and erasure of the flash memory. The FACI( flash application command interface) controls the FCU according to the specified FACI commands.

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nidhi singh
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nidhi singh
Asked: September 22, 2022In:
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RA4M1, SPI with DMA?

Hi, I search for a small example for SPI Master and DMA transfer. So that I can receive e.g. 15 bytes with DMA and get a transfer end to intrude/ message when it’s finished. Thanks in advance!

Hi,

I search for a small example for SPI Master and DMA transfer.
So that I can receive e.g. 15 bytes with DMA and get a transfer end to intrude/ message when it’s finished.

Thanks in advance!

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dmara4m1renesasRenesas Microcontrollerspi
  1. vikas Nagpal

    FSP4.0 supports DTC and DMAC transfer interface in the driver Add ther_spi driver to your design Add the DMAC transfer driver to the stack

    FSP4.0 supports DTC and DMAC transfer interface in the driver

    Add ther_spi driver to your design

    Add the DMAC transfer driver to the stack

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Techworld
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Techworld
Asked: August 22, 2022In:
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Why RA4W1 – SPI Interbyte Delay

I’m using Renesas FSP to set up the SPI module of an RA4W1 EVK as Master. I’m using burst mode( no negation of the SS between bytes) and there’s an”inter-byte” delay, as shown in figure below( taken from the MCU ...Read more

I’m using Renesas FSP to set up the SPI module of an RA4W1 EVK as Master. I’m using burst mode( no negation of the SS between bytes) and there’s an”inter-byte” delay, as shown in figure below( taken from the MCU datasheet). Is there anyway to get relieve of this delay? I know FSP allows setting the values for timepiece delay, SS negation delay, and coming access delay, but their minimal value is SPI_DELAY_COUNT_1, which results in a delay of 3 CLK cycles between bytes. Some SPI Slaves allow nonstop timepiece with no delay between bytes, which results in advanced outturn.

Thanks for any help you can give!

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delayra4w1spi
  1. Sandeep kumar

    The User's Manual states that you cannot change the SSL negation delay in the SPI module to less than one cycle. However, have you tried utilising the SCI module in SPI Master mode?

    The User’s Manual states that you cannot change the SSL negation delay in the SPI module to less than one cycle.

    However, have you tried utilising the SCI module in SPI Master mode?

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vsharma
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vsharma
Asked: July 30, 2022In:
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How to interface a PSoC (e.g. PSoC 63) with a WiFi module (e.g. CY43439)? Is this WiFi-host-driver agnostic to the hardware interface like SPI or SDIO?

How to interface a PSoC (e.g. PSoC 63) with a WiFi module (e.g. CY43439)?

Is this WiFi-host-driver agnostic to the hardware interface like SPI or SDIO?

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psocsdiospiwifi
  1. pallavi sharma

    For the wifi chip that you want to use, driver should have the support or implementation of the interface that you need. For 43439, both the SDIO and SPI interfaces are supported between host and WLAN chip in WHD.

    For the wifi chip that you want to use, driver should have the support or implementation of the interface that you need. For 43439, both the SDIO and SPI interfaces are supported between host and WLAN chip in WHD.

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Anonymous
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Anonymous
Asked: July 28, 2022In:
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 I wanted to clarify the difference between using the SCI module’s SPI pins as opposed to using the SPI pins that aren’t within the SCI module. I was wondering if you could explain why one would choose to use either ...Read more

 I wanted to clarify the difference between using the SCI module’s SPI pins as opposed to using the SPI pins that aren’t within the SCI module. I was wondering if you could explain why one would choose to use either the SPI inside of the SCI module, or use the independent SPI and some design considerations that would be included in making that decision. One more point of confusion for me was why there are pins dedicated to slave selection for SPI communication. To my understanding (which is quite limited), generally with other microcontrollers, you may use a simple GPIO as a slave selection pin, I was wondering if Renesas microcontrollers also had this option or if you have to use the slave selection pins given by the datasheet of the microcontroller.

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gpioscispi
  1. pallavi sharma

    The SCI supports a so-called "Simple SPI" mode that has far less capability than the std SPI peripheral.  From the hardware U/M: If your application requirements can be met by the Simple-SPI then it could be used.

    The SCI supports a so-called “Simple SPI” mode that has far less capability than the std SPI peripheral.  From the hardware U/M:

    If your application requirements can be met by the Simple-SPI then it could be used.

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vikas Nagpal
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vikas Nagpal
Asked: July 28, 2022In:
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Question 1: While using the Flash functions in flash_ops.c. It seems that the flash erase functionesp_err_t IRAM_ATTR spi_flash_erase_range(uint32_t start_addr, uint32_t size)is limited to erasing 32768 bytes at a time – is this True?The erase function does not return any ...Read more

Question 1:

While using the Flash functions in flash_ops.c. It seems that the flash erase function

esp_err_t IRAM_ATTR spi_flash_erase_range(uint32_t start_addr, uint32_t size)

is limited to erasing 32768 bytes at a time – is this True?

The erase function does not return any error – however I have a function that I am using to test the SPI flash by writing and reading back data. It only works if I erase smaller chunks at a time.

Question 2:
Do these functions support unaligned access yet?

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flash functionspiunaligned access
  1. pallavi sharma

    The spi_flash_erase_range() function should erase any size, as long as it's offset/size are a multiple of 4096 bytes and the region doesn't overflow the configured flash size. If the erase covers any 32KB aligned blocks, these are erased using the "block erase" function as this is faster than erasinRead more

    The spi_flash_erase_range() function should erase any size, as long as it’s offset/size are a multiple of 4096 bytes and the region doesn’t overflow the configured flash size.

    If the erase covers any 32KB aligned blocks, these are erased using the “block erase” function as this is faster than erasing 8x 4KB sectors individually.

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Anonymous
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Anonymous
Asked: July 25, 2022In:
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I have noticed that e2studio uses the term “simple SPI” for the SCI peripherals.  I am setting up a new board where I need two SPI connections for my RA4M3 board.  One to some motor drivers and one to non-QSPI ...Read more

I have noticed that e2studio uses the term “simple SPI” for the SCI peripherals.  I am setting up a new board where I need two SPI connections for my RA4M3 board.  One to some motor drivers and one to non-QSPI external flash.  I will use the one “standalone SPI” that is available, and then one of the SCI peripherals.

Are there any constraints I need to worry about?

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non-Qspi external flashra mcura4m3SCI peripheralsspi
  1. pallavi sharma

    The "simple SPI" mode of the SCI is significantly different than the SPI peripheral. For example the simple-SPI is limited to only 8-databits while the standalone-SPI supports many different bit lengths.  If your needs are met by what the simple-SPI supports there is no reason to avoid to using it.

    The “simple SPI” mode of the SCI is significantly different than the SPI peripheral.

    For example the simple-SPI is limited to only 8-databits while the standalone-SPI supports many different bit lengths.  If your needs are met by what the simple-SPI supports there is no reason to avoid to using it.

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Rutuja
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Rutuja
Asked: July 22, 2022In:
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In our project, the parser reads the G-code from the SD card through the SPI interface, using a usual SD.h library. The problem is that regardless of the size of the SD card buffer, the SPI reads 4092 bytes every ...Read more

In our project, the parser reads the G-code from the SD card through the SPI interface, using a usual SD.h library. The problem is that regardless of the size of the SD card buffer, the SPI reads 4092 bytes every time, puts them in the DMA buffer, and reads the next 4092 only when the buffer is free. Because of this, the time for reading g-commands is extremely uneven. Most are read in 20µs, but each 146th is read in over 4500µs. (The average length of g-command is 28 bytes, so 4092/28=146.)
4500µs is approximately equal to the transmission of 4KB at 10MHz. This is a terribly unacceptable time that kills all the advantages of the speed of the microcontroller.

Is there a way to reduce SPI buffer size using arduino IDE? I tried to re-initialize SPI with this construction:

#include “driver/spi_master.h”

#define PIN_NUM_MISO 19

#define PIN_NUM_MOSI 23

#define PIN_NUM_CLK 18 static void spi_init() { spi_bus_config_t buscfg; memset(&buscfg, 0, sizeof(spi_bus_config_t)); buscfg.miso_io_num=PIN_NUM_MISO; buscfg.mosi_io_num=PIN_NUM_MOSI; buscfg.sclk_io_num=PIN_NUM_CLK; buscfg.quadwp_io_num=-1; buscfg.quadhd_io_num=-1; buscfg.max_transfer_sz=64; //default to 4092 if 0 spi_bus_initialize(VSPI_HOST, &buscfg, 1); //DMA channel 1 };

This probably works (message “E (280387) spi: spi_bus_initialize(756): SPI bus already initialized” in console), but in general, the situation does not change. Each 146th g-command is still read in 4500µs. SPI bus is still working through some huge 4KB buffer. And I have totally no idea how to divide it into small chunks of 64-128 bytes.

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dma bufferg-codespi
  1. pallavi sharma

    If you use a RTOS-aware structure (like a ringbuffer, queue, whatever) then you don't need to delay: the push into the buffer will block for you while there's no room available. The amount of elements in a ringbuffer is limited by its size, so you can double, triple, however-many-le buffer the thingRead more

    If you use a RTOS-aware structure (like a ringbuffer, queue, whatever) then you don’t need to delay: the push into the buffer will block for you while there’s no room available. The amount of elements in a ringbuffer is limited by its size, so you can double, triple, however-many-le buffer the things by simply increasing the size of the ringbuffer. Also, perhaps good to mention that by ‘ringbuffer’ I specifically mean the esp-idf ringbuffer construct, as that is RTOS-aware. If you use the bytebuffer mode of that, it would be good.

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vsharma
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vsharma
Asked: July 12, 2022In:
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In Renesas RA4M3 with an SCI SPI setup, we have MOSI rising up to 3.7 V instead of 3.3V. After verifying that all input voltage to the processor is 3.3V and testing it with nothing connected to the SCI SPI ...Read more

In Renesas RA4M3 with an SCI SPI setup, we have MOSI rising up to 3.7 V instead of 3.3V. After verifying that all input voltage to the processor is 3.3V and testing it with nothing connected to the SCI SPI as well we could not find reason for MOSI rising up to 3.7V.

Any insight on why this happens?

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mosira4m3renesasscispi
  1. pallavi sharma

    It seems that the motor driver board is sourcing voltage and current into the EVK. 

    It seems that the motor driver board is sourcing voltage and current into the EVK. 

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