How do we change the UART BR in runtime?
How do we change the UART BR in runtime?
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There are basically two way to change the UART baud rate at run-time. It depends how you allocated the UART. If you allocated by PDL-method (ie. In the PSoC Creator TopDesign or Modustoolbox Device Configurator [design.modus]) then use the PDL SysClk API calls: Configure Baud Rate To get the UARTRead more
There are basically two way to change the UART baud rate at run-time. It depends how you allocated the UART.
If you allocated by PDL-method (ie. In the PSoC Creator TopDesign or Modustoolbox Device Configurator [design.modus]) then use the PDL SysClk API calls:
Configure Baud Rate
To get the UART to operate with the desired baud rate, the clk_scb frequency and the oversample must be configured. Use the SysClk (System Clock) driver API to configure clk_scb frequency. Set the oversample parameter in configuration structure to define the number of the SCB clocks within one UART bit-time.
* For clk_peri = 50 MHz, select divider value 36 and get SCB clock = (50 MHz / 36) = 1,389 MHz.
* Select Oversample = 12. These setting results UART data rate = 1,389 MHz / 12 = 115750 bps.
*/
Cy_SysClk_PeriphSetDivider (UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER, 35UL);
Cy_SysClk_PeriphEnableDivider(UART_CLK_DIV_TYPE, UART_CLK_DIV_NUMBER);
Refer to the technical reference manual (TRM) section UART sub-section Clocking and Oversampling to get information about how to configure the UART to run with desired baud rate.
link: file:///C:/Program%20Files%20(x86)/Cypress/PDL/3.1.1/doc/pdl_api_reference_manual/html/group__group_…
If you allocated the UART by the HAL-method use:
cyhal_uart_set_baud() link: Hardware Abstraction Layer (HAL)
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