I’ve designed a very smooth and low ripple 5V force for my board. This gets coupled through an LDO 3.3 V controller to feed the ESP32 (same as most boards out there). When the ESP32 transmits WiFi, I see a 50- 100mV drop in the 3.3 V rail and it’s being coupled through to the 5V side of the 3.3 V reg.
Large electrolytic caps on the 5V side and the 3.3 V side bettered it greatly (to the 50- 100mV measured result) but I would like to see further improvements.
Most 3.3 V LDO regs all appear to have the same/similar load regulation characteristics so I’m not yet convinced a change in reg will resolve the issue. Having a 16-bit ADC on board means I’m very sensitive to voltage changes on the 5V rail.
Has anyone overcome this issue already?