Looking at the ESP32- S3 datasheet section 3.5.2 Serial supplemental Interface( SPI), in the SPI2 Generalpurpose SPI( GPSPI) mode part it’s mentioned that SPI2 can do DDR at 40Mhz while in half duplex mode.
In the design i’ve a SPI slave chip that does DDR on the MISO line, as in MISO line needs to be sampled at both edges of the SCLK line. It’s not a flash/ ram chip, so I need to drive the SPI2 in the general purpose mode.
I wanted to confirm that this is what the datasheet says, but looking at API docs for ESP- IDF for ESP32- S3 only talks about SPI DDR for external flash modules.
Can someone clarify, can I use SPI2 in general purpose master mode with half duplex, to sample the MISO line on both edges of SCLK?
It does have a DDR feature, but I do not think this point is in the driver yet. Can you share what chip you are trying to communicate with? I can tell the driver team what to focus on if I file an issue to apply this.
It does have a DDR feature, but I do not think this point is in the driver yet. Can you share what chip you are trying to communicate with? I can tell the driver team what to focus on if I file an issue to apply this.
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