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Around ROM_Test_Failure in IEC 60730/60335 Self Test Library for RA2L1


I have a custom plan board with R7FA2L1AB2DFP MCU. I compiled the test software without any problems. But when debugging, it enters the error recognized loop due to the ROM test mistake. To generate the addcrc.srec file, I utilized the same settings as within the CRCcalcCmd256KB.txt file. Am I making a mistake somewhere?

CRC calculate Original.srec -fill 0xFF 0x00000 0x040000 # 256KB ROM fill by 0xFF

-crop 0x00000 0x03FFFC #CRC calculate area

-STM32-le 0x03FFFC#

-crop 0x3FFFC 0x40000 Original.srec

-fill 0xFF 0x000000 0x03FFFC#

-fill 0xFF 0x0000 0x0FFFC

-Output addcrc.srec

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